|
Artian-Apps
|
Software manager for thinclient
|
2024-02-14 09:30:33 +03:30 |
|
699-pin Socket.png.jpg
|
This photo is for the HTTP Server document
|
2024-02-14 15:08:32 +03:30 |
|
699-pin connector.png
|
This photo is for the HTTP Server document
|
2024-02-14 15:08:32 +03:30 |
|
Artian-server-structure.png
|
This photo is for the document "Analysis of the main server board".
|
2024-02-17 07:19:38 +03:30 |
|
ArtianDes.png
|
Add picture for test
|
2023-11-29 08:08:43 +03:30 |
|
Benchmark Comparison (3).png
|
This photo is for the document "Primary comparison between RK3399 and RK3588S".
|
2024-02-18 10:22:33 +03:30 |
|
Benchmark comparison (2).png
|
This photo is for the document "Primary comparison between RK3399 and RK3588S".
|
2024-02-18 10:13:32 +03:30 |
|
Benchmark comparison.png
|
This photo is for the document "Primary comparison between RK3399 and RK3588S".
|
2024-02-18 10:13:32 +03:30 |
|
Figure (12).png
|
This picture is for the document " Comparison of FLY-by architecture with T-Double in PCB layout routing for DDR4 memory ".
|
2024-02-17 09:28:33 +03:30 |
|
Figure (13).png
|
This picture is for the document " Comparison of FLY-by architecture with T-Double in PCB layout routing for DDR4 memory ".
|
2024-02-17 09:28:33 +03:30 |
|
Figure (14).png
|
This picture is for the document " Comparison of FLY-by architecture with T-Double in PCB layout routing for DDR4 memory ".
|
2024-02-17 09:28:33 +03:30 |
|
Figure (15).png.jpg
|
This picture is for the document " Comparison of FLY-by architecture with T-Double in PCB layout routing for DDR4 memory ".
|
2024-02-17 09:28:33 +03:30 |
|
Figure 2. Internal structure of the RTL8370 chip.png
|
This photo is for the document "Analysis of the main server board".
|
2024-02-17 07:19:38 +03:30 |
|
How Get IP.png
|
These photos are for the document "Analysis of slave nodes in native server".
|
2024-02-18 07:30:18 +03:30 |
|
Module-Carrier Board.png
|
This photo is for the HTTP Server document
|
2024-02-14 15:08:32 +03:30 |
|
PCB-ThinClient-image.png
|
This photo is for the HTTP Server document
|
2024-02-14 15:08:32 +03:30 |
|
Photo of Schema.jpg
|
This photo is for the "Parts Dimensions Table" document.
|
2024-02-17 10:24:42 +03:30 |
|
Photo of the size table of parts.jpg
|
This photo is for the "Parts Dimensions Table" document.
|
2024-02-17 10:24:42 +03:30 |
|
Picture1.png
|
This photo is for the HTTP Server document
|
2024-02-14 09:33:33 +03:30 |
|
Picture2.png
|
This photo is for the HTTP Server document
|
2024-02-14 09:33:33 +03:30 |
|
Picture3.jpg
|
This photo is for the "Parts Dimensions Table" document.
|
2024-02-17 10:24:42 +03:30 |
|
Picture3.png
|
This photo is for the HTTP Server document
|
2024-02-14 09:33:33 +03:30 |
|
Picture4.jpg
|
This photo is for the "Parts Dimensions Table" document.
|
2024-02-17 10:24:42 +03:30 |
|
Picture5.jpg
|
This photo is for the "Parts Dimensions Table" document.
|
2024-02-17 10:24:42 +03:30 |
|
Schematic-699 pin.png
|
This photo is for the HTTP Server document
|
2024-02-14 15:08:32 +03:30 |
|
Scope.png
|
These photos are for the document "Analysis of slave nodes in native server".
|
2024-02-18 07:30:18 +03:30 |
|
Server & Client.jpg
|
These photos are for the document "Analysis of slave nodes in native server".
|
2024-02-18 07:30:18 +03:30 |
|
Table (1) Configure Pins.png
|
This Table is for the document "Analysis of the main server board".
|
2024-02-17 07:42:12 +03:30 |
|
table1( Description ).png
|
This photo is for the HTTP Server document
|
2024-02-14 15:08:32 +03:30 |
|
table1-1.png
|
This photo is for the HTTP Server document
|
2024-02-14 15:08:32 +03:30 |
|
table1.png
|
This photo is for the HTTP Server document
|
2024-02-14 15:08:32 +03:30 |
|
table2( Description ).png
|
This photo is for the HTTP Server document
|
2024-02-14 15:08:32 +03:30 |
|
table2-1.png
|
This photo is for the HTTP Server document
|
2024-02-14 15:08:32 +03:30 |
|
table2.png
|
This photo is for the HTTP Server document
|
2024-02-14 15:08:32 +03:30 |
|
void exportGPIO.png
|
These photos are for the document "Analysis of slave nodes in native server".
|
2024-02-18 07:30:18 +03:30 |
|
شکل 1. All signals in the DATA 6 Group are routed “the same way”, using the same topology and layer transitions..png
|
This picture is for the document " Comparison of FLY-by architecture with T-Double in PCB layout routing for DDR4 memory ".
|
2024-02-17 08:41:13 +03:30 |
|
شکل 2. Blankets and PCB directives are used to create net class groups for DDR3 routing guidelines..png
|
This picture is for the document " Comparison of FLY-by architecture with T-Double in PCB layout routing for DDR4 memory ".
|
2024-02-17 08:41:13 +03:30 |
|
شکل 3. Assigning different colors to each group can make routing easier to mentally follow..png
|
This picture is for the document " Comparison of FLY-by architecture with T-Double in PCB layout routing for DDR4 memory ".
|
2024-02-17 08:41:13 +03:30 |
|
شکل 4. Choosing a correct via size can help save space for more tracks..png
|
This picture is for the document " Comparison of FLY-by architecture with T-Double in PCB layout routing for DDR4 memory ".
|
2024-02-17 08:41:13 +03:30 |
|
شکل 5. Two or three tracks can fit between microvias, in the same space needed for one track between Through Hole Vias..png
|
This picture is for the document " Comparison of FLY-by architecture with T-Double in PCB layout routing for DDR4 memory ".
|
2024-02-17 08:41:13 +03:30 |
|
شکل 6. Some of the Address, Command, and Control tracks have to be routed under the pads of the “closest groups”..png
|
This picture is for the document " Comparison of FLY-by architecture with T-Double in PCB layout routing for DDR4 memory ".
|
2024-02-17 08:41:13 +03:30 |
|
شکل 7. Free space left under groups routed with microvias can be used to fanout the “closest groups”..jpg
|
This picture is for the document " Comparison of FLY-by architecture with T-Double in PCB layout routing for DDR4 memory ".
|
2024-02-17 08:41:13 +03:30 |
|
شکل 8..png
|
This picture is for the document " Comparison of FLY-by architecture with T-Double in PCB layout routing for DDR4 memory ".
|
2024-02-17 08:41:13 +03:30 |
|
شکل 9. Fly-by topology for DDR layout and routing.png
|
This picture is for the document " Comparison of FLY-by architecture with T-Double in PCB layout routing for DDR4 memory ".
|
2024-02-17 08:41:13 +03:30 |
|
شکل 10. Double-T topology for DDR layout and routing.png
|
This picture is for the document " Comparison of FLY-by architecture with T-Double in PCB layout routing for DDR4 memory ".
|
2024-02-17 08:41:13 +03:30 |
|
شکل 11. The DQS lines in this SODIMM module are routed on the same layer.png
|
This picture is for the document " Comparison of FLY-by architecture with T-Double in PCB layout routing for DDR4 memory ".
|
2024-02-17 08:41:13 +03:30 |
